102 F.3d 534 | Fed. Cir. | 1997
41 U.S.P.Q.2d 1023
Patricia WIENER, Plaintiff-Appellant,
v.
NEC ELECTRONICS, INC. and NEC Corporation, Defendants-Appellees.
No. 96-1052.
United States Court of Appeals,
Federal Circuit.
Dec. 6, 1996.
Rehearing Denied Jan. 10, 1997.
Clarence E. Eriksen, Arnold, White & Durkee, Houston, TX, argued, for plaintiff-appellant. With him on the brief were Christopher R. Benson, Richard L. Stanley, and Timothy M. Honeycutt.
Charles D. Chalmers, Skjerven, Morrill, MacPherson, Franklin & Friel, San Jose, CA, argued, for defendants-appellees. With him on the brief were Justin T. Beck, and Scott D. Minden. Of counsel was Kimberly P. Zapata.
Before MICHEL, RADER, and SCHALL, Circuit Judges.
RADER, Circuit Judge.
Decision
Appellant, Patricia Wiener, appeals from a certified final judgment after the United States District Court for the Northern District of California granted summary judgment of non-infringement in favor of appellees, NEC Electronics, Inc. and NEC Corporation (collectively, NEC). Although the trial court improperly interpreted some claim terms, and improperly analyzed the issues of fact on marking, a proper claim interpretation still compels this court to affirm the grant of summary judgment of non-infringement and vacate the holding concerning marking.
Background
On November 6, 1973, U.S. Patent No. 3,771,145--entitled "Addressing an Integrated Circuit Read-Only Memory" (the '145 patent) issued to Patricia Wiener. The '145 patent discloses a means for addressing a memory array or matrix in a read-only memory (ROM) device. The patent recites a memory in the form of a matrix of columns and rows. At the intersection of each row and column the memory stores one unit of data called a bit. Each bit has a unique address specified by its corresponding row and column.
To retrieve the information from the memory array, a user first selects a particular row by applying an address input signal to the ROM. This signal identifies the row the user wishes to access. The user may then extract data from the selected row in eight-bit (byte) segments, each of which corresponds to eight columns of the seventy-two columns in the matrix. The claimed device includes a counter on the integrated circuit that enables the extraction of successive bytes (all seventy-two bits on the row, also known as words) from the columns with a single row addressing signal. The invention then routes these successive bytes into an output buffer for external use. This claimed counter provides two advantages. First, it allows extraction of data at an increased speed. Second, it allows the extraction to commence at any byte on the addressed row, not just from the first byte as in previous technologies.
Even though the '145 patent includes twenty-three claims, only four claims (9, 10, 12, and 13) are at issue in this appeal. Claim 9 states:
9. In a memory circuit on an integrated circuit chip having plural, individually addressable word locations, each word location holding a plurality of bytes, each byte having a plurality of bits, a read-out circuit comprising:
first means on the chip for defining a data matrix having addressing rows and data columns, the intersection of a row and of a column defining a memory location;
second means on the chip responsive to a first, externally applied addressing code and connected for addressing one of the rows, pursuant to such addressing the content of the memory locations is available on the columns;
third means on the chip connected for sequentially calling on the columns for one byte at a time and providing bit value defining signals representing one respective byte for external extraction of the bytes as provided in particular sequence;
fourth means on the chip connected to the third means for establishing a particular beginning of a byte call sequence, and
fifth means on the chip for establishing a particular end for the byte call sequence.
Claim 10 depends from claim 9. Claim 12, the other independent claim at issue, reads:
12. In a memory on an integrated circuit chip having a plurality of word locations, each word location holding a plurality of bytes, each byte having a plurality of bits, the combination comprising:
first means on the chip defining a data matrix that includes a plurality of columns of bit cells, each column of cells including a bit extraction column, one extraction column per bit position in a word location, the data matrix including a plurality of addressing rows, one row per word location and coupled to all columns of cells, one bit per column of cells;
second means on the chip defining a decoder network responsive to address bits applied externally to the chip, and having a plurality of outputs respectively coupled to the rows of the plurality, and including means to provide an addressing signal on one of the rows in response to a particular combination of applied address bits, so that the matrix applies the bits of the addressed location to the extraction columns and sustains the bits therein;
third means on the chip defining a counter progressing at a particular sequence thereby providing sequentially different enabling signals, while the data bits are sustained on said extraction columns;
fourth means connected to all of the extraction columns and to the third means and selecting the bits on some of the extraction columns in parallel and in response to one of the enabling signals from the counter, and providing a string of bytes in response to progression of the counter and of the enabling signals as provided by the counter; and
fifth means for presenting the bits of a byte concurrently and the bytes as sequentially provided by operation of the fourth means, as a byte string for use external to the chip.
Claim 13 depends from claim 12.
The alleged infringer, NEC, makes and sells memory chips called Video Random Access Memories (VRAMs). Like the patented invention, the accused devices are integrated circuit memories with data storage locations arranged in rows and columns. Further, the VRAM, again like the patented invention, stores a data bit at each row-column intersection. Data extraction in the VRAM commences by first addressing a row. At that point, however, the VRAM does not access the columns on the memory matrix byte-by-byte. Instead, a gate or latch closes or completes the circuit, which transfers the data on all columns within the selected row into an adjoining data register. The VRAM then disconnects the gates or latches to electrically isolate the data register from the memory array. The user then extracts data from the data register byte-by-byte. Simultaneously, new information is read into the columns of the memory array, in contrast to the '145 patent in which the data in the matrix is static.
This summary of the facts highlights the dispute over the meaning of claims 9 and 12. NEC asserts that its products have no mechanism to read data directly from the columns in the memory matrix, as allegedly required by the third means in claim 9 of the '145 patent. NEC contends that its VRAM does not call "on the columns for one byte at a time" as required by claim 9. NEC also asserts that its products have no mechanism on the chip to establish the particular beginning or end of a byte string extracted from a row of the memory matrix, as allegedly required by the fourth and fifth means of claim 9.
Conversely, Wiener asserts that the NEC products contain the third, fourth, and fifth means of claim 9. Specifically, Wiener contends a user extracts data from the data register that, according to Wiener, is part of the column of memory. Furthermore, Wiener argues that the NEC products contain mechanisms on the chip which establish the particular beginning and end of a byte string.
The dispute over the meaning of claim 12 is essentially identical to that concerning claim 9. Wiener contends that the proper interpretation of "extraction column" includes the data register latches and transfer gates between the data matrix and the read select circuits. NEC, on the other hand, urges an interpretation limiting the extraction columns to the area bounded by the data matrix.
After receiving recommendations from a special master, the district court considered these issues on cross-motions for summary judgment. The trial court granted NEC's motion for non-infringement and denied Wiener's motion for infringement. In reaching this result, the district court construed the terms "data column," "column," and "extraction column" to describe "only the passive elements, the adjacent P-zones, within the data matrix of the '145 patent." The district court then adopted the special master's finding:
The data in the Accused Products is transmitted from the memory matrix to the data register simultaneously, then read byte-by-byte from the data register, rather than from the data columns. Accordingly, the Accused Products lack any means for "sequentially calling on the columns for one byte at a time," and do not literally infringe claim 9....
....
The Accused Products do not meet the Third Means under the doctrine of equivalents.
Wiener v. NEC Elec., Inc., No. C 91-20843 JW, 1995 WL 429204, at * 5 (N.D.Cal. July 17, 1995). The district court also adopted a similar chain of special master findings in rejecting infringement under the fourth means of claim 9. Id. at * 5-6.
With respect to the fifth means of claim 9, the district court again adopted special master findings:
The Accused Products do not literally infringe the Fifth Means because the Accused Products contain no element on the chip for establishing an end to the byte string sequence....
[T]he Accused Products end the byte string sequence only by means external to the chip, and only internal means on the chip are claimed in the Fifth Means.
Id. at * 6. Thus, the district court rejected infringement under claim 9 of the '145 patent.
Similarly, the district court adopted findings rejecting infringement under the third and fourth means of claim 12. With regard to the third means, the court found that "in the Accused Products bits are not sustained on the extraction columns in the data matrix while the counter is counting." Id. at * 7. This reasoning likewise was applied to the fourth means. In sum, the district court rejected both literal infringement and infringement by equivalents under all of the asserted claims of the '145 patent. On September 13, 1995, the district court certified this case for immediate appeal under Fed.R.Civ.P. 54(b).
Previously, in June 1994, the court had addressed the issue of marking. NEC moved for partial summary judgment alleging that Wiener did not mark patented devices sold to Pacer Systems and Texas Instruments, Inc. (TI) in violation of 35 U.S.C. § 287 (1994). The district court adopted the special master's recommendations, including a series of allegedly undisputed facts, and granted NEC's motion. See Wiener v. NEC Elec., Inc., No. C 91-20843 JW, at 3-4 (N.D. Cal. June 8, 1994) (unpublished).
Wiener's company, Anarm, sold memory devices covered by the '145 patent to Pacer Systems, Inc. (Pacer) in September 1974. NEC's motion alleged that these few devices were not properly marked. In November 1973, however, Wiener's attorneys had advised her of the marking requirement. In turn, Wiener had informed Vincent Leto, her chief technician, of his responsibility to mark all patented devices. At his deposition, Leto testified that he had no reason to believe that he had not carried out Wiener's instructions, but he could not precisely recall whether he had properly marked the chips twenty years earlier. Moreover, Jerome Wiener, appellant's husband, stated in a declaration that on a visit to the Anarm facility he had witnessed Leto marking the chips and had seen several hand-marked chips.
As to TI, on August 1, 1990, Wiener granted a license to TI in settlement of a lawsuit for infringement of the '145 patent. The terms of the license did not require TI to mark the products. However, the period of TI's license--August 1, 1990 through November 6, 1990, the date the patent expired--came after Wiener had already notified NEC by letter of the alleged infringement. Notwithstanding these disputed facts or facts favoring judgment for Wiener, the district court held that "construing the undisputed facts in light most favorable to Wiener, she fails to prove by a preponderance of the evidence that patented chips were [properly] marked."
Discussion
In this case, the district court granted summary judgment of non-infringement, finding no genuine issues of material fact precluding legal judgment. This court reviews the grant of summary judgment as a question of law. See Winner Int'l Corp. v. Wolo Mfg. Corp., 905 F.2d 375, 376, 15 USPQ2d 1076, 1077 (Fed.Cir.1990). Also, because the parties dispute the meaning of terms in the claims of the patent, this court reviews the district court's order under the requirements of Markman v. Westview Instruments, Inc., --- U.S. ----, ----, 116 S.Ct. 1384, 1395, 134 L.Ed.2d 577 (1996) (noting that claim construction " 'falls somewhere between a pristine legal standard and a simple historical fact' ") (quoting Miller v. Fenton, 474 U.S. 104, 114, 106 S.Ct. 445, 451-52, 88 L.Ed.2d 405 (1985)).
To resolve infringement, a court determines the scope and meaning of the claims and assesses whether the accused device falls within those bounds (the latter being a question of fact, see infra ). See Becton Dickinson & Co. v. C.R. Bard Inc., 922 F.2d 792, 796, 17 USPQ2d 1097, 1099 (Fed.Cir.1990). To prove infringement, the plaintiff must show that the accused device includes every limitation of the claim or an equivalent of each limitation not literally met. See id.
The language of the claims (plus equivalents of the claimed invention) defines the bounds of the patentee's exclusive rights. See Bell Communications Research, Inc. v. Vitalink Communications Corp., 55 F.3d 615, 619-20, 34 USPQ2d 1816, 1819 (Fed.Cir.1995) ("First, and most importantly, the language of the claim defines the scope of the protected invention."); Yale Lock Mfg. Co. v. Greenleaf, 117 U.S. 554, 559, 6 S.Ct. 846, 848, 29 L.Ed. 952 (1886) ("The scope of letters-patent must be limited to the invention covered by the claim, and while the claim may be illustrated it cannot be enlarged by language used in other parts of the specification."). To construe the meaning of terms within the claims, a court may consult the patent specification and the administrative record at the Patent and Trademark Office leading to issuance of the patent. See Unique Concepts, Inc. v. Brown, 939 F.2d 1558, 1561, 19 USPQ2d 1500, 1503 (Fed.Cir.1991). Ultimately, a court must construe the claim language according to the standard of what those words would have meant to one skilled in the art as of the application date. See W.L. Gore & Assocs., Inc. v. Garlock, Inc., 721 F.2d 1540, 1556, 220 USPQ 303, 316 (Fed.Cir.1983).
NEC admits that its VRAM contains elements that fall within the meaning of the preamble to claim 9, as well as within the meaning of the first and second means' limitations. This focuses the infringement question on the third means of claim 9, which states:
third means on the chip connected for sequentially calling on the columns for one byte at a time and providing bit value defining signals representing one respective byte for external extraction of the bytes as provided in particular sequence
(Emphasis added.) This claim language requires some structure that calls "on the columns for one byte at a time."
The context of the entire claim provides a reference for the meaning of "columns" in the quoted claim language. The preamble of claim 9 clarifies that the invention operates within "a memory circuit on an integrated circuit" with "individually addressable word locations." The first means in claim 9 specifies that this memory circuit is a "data matrix having addressing rows and data columns." According to the first means language, "the intersection of a row and of a column" define a memory location. The second means phrase states that "the content of the memory locations is available on the columns." Thus, the context of the claim shows that a "column" is part of the data matrix "on the chip" that encodes and retains information.
The specification confirms that the "columns" are structures within the memory matrix on the chip. The specification states that "[the matrix columns] are established by and between pairs of runs of P-zones extending orthogonal to the rows." A P-zone is a region in the semiconductor structure in which the ROM is built. P-zones at selected locations within the N-type semiconductor substrate create an integrated circuit. In the instant case, the data columns are two P-zones side-by-side within the N-type substrate. One of these P-zones is permanently grounded as a reference node. The other P-zone, the extraction column, can either carry a positive charge or be held at ground. In each row, a transistor forms or remains unformed between P-zones to encode data at that particular row-column intersection.
The district court's proceedings strove to establish whether "column" means only the passive elements of the dual P-zone structure or also includes active elements, such as the transistors that may be electrically coupled to the passive elements. Wiener argues that a broad understanding of "column" includes not only the active P-zone elements, but also the latches on NEC's data register.
The district court, adopting the findings of the special master, construed "columns" to include only passive elements, i.e., the adjacent P-zones. For support, the district court looked to the specification. For example, the specification indicates:
Some of these runs of P-zones are permanently connected to ground; they are selected so that each P-zone run which is not grounded, is flanked by but one run that is grounded. Two such P-zones define a data column.
In defining "column," the district court also pointed to statements in the specification such as "[a]ll non-(permanently) grounded P-zones define memory extraction columns," and "[e]ach data column is established by two adjacent P-zones, one thereof serving as a data extraction column."
The district court interpreted "column" too restrictively in narrowing that term to only passive elements within the structure of the data matrix. In the phrases noted by the district court, the specification describes the physical boundaries of the columns. The columns indeed fall on and between the P-zones and are thus "defined" by those regions. Those specification citations, however, do not describe the entire function of the "columns." The transistor, an active element bridging adjacent P-zones, also falls within the definition of "column." Indeed, the columns would not function to store information without the operation of transistors. In that sense, the columns include not only the passive elements, but also may include the active elements.
However, the district court's interpretation error proves harmless. Although "columns" can include active elements, they do not include all active elements found anywhere on the output paths of a data bit. Rather, the claims themselves further define the terms "data column" and "extraction column." The first means of claim 9 describes a memory matrix with "addressing rows and data columns." The second means adds that "the content of the memory locations is available on the columns." Therefore, as defined in the claim itself, the claimed columns are located on the data matrix.
Claim 12's "extraction column" carries similar limitations. The first means of claim 12 states that the data matrix includes "a plurality of columns of bit cells, each column of cells including a bit extraction column." Thus, once again, the claim language places the columns on the data matrix.
The specification supports this interpretation of the location of the columns. For example, the specification describes the data column as "established by two adjacent P-zones, one thereof serving as a data extraction column." Thus, the columns as defined by the patent, both data columns and extraction columns, are within and limited to the data matrix. With this understanding, the third means of claim 9--which recites a means "for sequentially calling on the columns for one byte at a time"--requires extraction of data from within the data matrix byte-by-byte.
In most cases, upon detecting an error in claim interpretation, this court would remand for a finding on infringement. See Mannesmann Demag Corp. v. Engineered Metal Prods. Co., 793 F.2d 1279, 1282, 230 USPQ 45, 46 (Fed.Cir.1986) (determining infringement is a question of fact). Where the parties do not dispute the technical functioning of the accused device and application of the interpreted claims to the accused device does not create further disputes, however, this court may proceed from claim interpretation to analysis of infringement.
To prove infringement, the patentee must show that the accused device has every limitation either literally or by an equivalent. See Laitram Corp. v. Rexnord, Inc., 939 F.2d 1533, 1535, 19 USPQ2d 1367, 1369 (Fed.Cir.1991). As discussed above, the claim language locates the columns, both data columns and extraction columns, on the data matrix. In this case, the accused VRAMs read bytes of information from the data register, which is outside of and isolated from the data matrix Accordingly, the accused devices lack any means for "sequentially calling on the columns for one byte at a time." Thus, the accused VRAMs do not literally infringe claim 9 for lack of the third means.
An accused device outside the literal meaning of the claims may still infringe by equivalents if it contains only an insubstantial change from the patented invention. See Hilton Davis Chem. Co. v. Warner-Jenkinson Co., 62 F.3d 1512, 1521-22, 35 USPQ2d 1641, 1648 (Fed.Cir.1995) (en banc) (holding that "a finding of infringement under the doctrine of equivalents requires proof of insubstantial differences between the claimed and accused products"), cert. granted, --- U.S. ----, 116 S.Ct. 1014, 134 L.Ed.2d 95 (1996). A patentee may prove this insubstantial change by showing that the accused device performs substantially the same function, in substantially the same way, to produce substantially the same result as the claimed invention. See Graver Tank & Mfg. Co. v. Linde Air Prods. Co., 339 U.S. 605, 608, 70 S.Ct. 854, 856, 94 L.Ed. 1097 (1950). Even under infringement by equivalents, however, the protection of a patent may not "embrace a structure that is specifically excluded from the scope of the claims." See Dolly, Inc. v. Spalding & Evenflo Cos., 16 F.3d 394, 400, 29 USPQ2d 1767, 1771 (Fed.Cir.1994).
In Dolly, this court examined a patent for a portable, adjustable child's chair. In its analysis of the claims, this court determined that the claim expressly recited a "stable rigid frame." Specifically, the claim limitation called for "a stable rigid frame which is formed in part from said side panels and which along with said seat panel and said back panel provides a body supporting feature, said stable rigid frame being self-supporting and free-standing, whereby said child's chair is readily portable and easily stored." Id. at 396. Therefore, the literal language of the claims required the chair to have a stable rigid frame separate from the seat and back panels. 16 F.3d at 398. Forming the stable rigid frame without the seat and back panels was an express limitation of the claim. Id.
While this court acknowledged that the doctrine of equivalents does not require a one-to-one correspondence of components, see, e.g., Corning Glass Works v. Sumitomo Electric U.S.A., 868 F.2d 1251, 1256, 9 USPQ2d 1962, 1965 (Fed.Cir.1989), this claim contained a limitation (stable rigid frame apart from the seat and back panels) which this court could not ignore during its doctrine of equivalents' analysis. Id. at 398-99. Therefore, a chair that forms a stable rigid frame with the seat and back panels could never constitute an insubstantial difference.
In the instant case, claim 9 contains an explicit requirement that the third means "call on the columns for one byte at a time." These columns, as noted earlier, are on the data matrix. Because the VRAM does not call on columns on the data matrix, it does not have an element that functions as required by the third means in the claim. Although the VRAM's data register may have "columns" similar to the columns claimed in the patent, the columns in the patent are on the data matrix. The VRAM's "columns" are not. As in Dolly, the required structure is specifically excluded. This court could not extend protection to the VRAM without ignoring the meanings and limitations of the language of claim 9. See Dolly, 16 F.3d at 398 ("The doctrine of equivalents is not a license to ignore claim limitations.").
In this case, the VRAMs do not contain an equivalent for each element of the claim. Specifically, the columns of the data matrix are not "called upon" to read bytes of information. Although the accused device may call upon other columns elsewhere, the claim requires the third means to call upon columns on the data matrix. This difference is not insubstantial. Even if the accused device performs a substantially similar function and reaches a substantially similar result, this court cannot overlook the clear language of this limitation of the claims. Pennwalt Corp. v. Durand-Wayland, Inc., 833 F.2d 931, 934, 4 USPQ2d 1737, 1739 (Fed.Cir.1987) (in banc). Therefore, in the absence of an equivalent for the third means, the accused devices do not infringe under the doctrine of equivalents.
Wiener attempts to create an issue of fact with the conclusory declaration of Mr. Eklund about equivalency. Because Mr. Eklund's statements rest on an incorrect claim interpretation, however, they do not create a factual dispute. Since Hilton Davis requires the patentee to prove insubstantial differences, 62 F.3d at 1521, and further, because, under Celotex v. Catrett, 477 U.S. 317, 322, 106 S.Ct. 2548, 2552, 91 L.Ed.2d 265 (1986), to survive a motion for summary judgment, the non-movant must make a sufficient showing that genuine issues of material fact exist on issues in which the non-movant bears the burden of proof, Wiener's claim of equivalents fails because she has not presented "substantial evidence" regarding equivalency. No lesser evidence can suffice. Her only relevant evidence, her expert's declaration, is too conclusory to constitute substantial evidence.
As to infringement of claim 12, a similar analysis applies. Once again, NEC does not contest that its products meet the requirements of the first and the second means. The third means of claim 12 provides:
third means on the chip defining a counter progressing at a particular sequence thereby providing sequentially different enabling signals, while the data bits are sustained on said extraction columns.
(Emphasis added.)
As with claim 9, supra, claim 12's extraction columns are within the data matrix. In the accused device, however, the data bits are not on the extraction columns while the counter operates as disclosed in claim 12. Instead, the VRAM transfers the data bits to the data register outside of the data matrix. This transfer away from the data matrix defeats literal infringement of claim 12 because the accused products do not contain the third means. Likewise, because a specific claim limitation is totally missing in the accused devices, i.e. performance of counter function while data bits are sustained on the extraction columns, the accused devices do not infringe under the doctrine of equivalents.
Finally, in view of this court's claim interpretation and findings on infringement, the district court's resolution of the marking issue in the face of genuinely disputed issues of fact amounts to harmless error. Wiener offered the statements of two individuals, Vincent Leto and Jerome Wiener, to testify that the devices sold to Pacer were marked by hand in pen and ink. Thus, viewing the evidence in the light most favorable to the non-movant with all justifiable inferences drawn in Wiener's favor, a reasonable fact finder could find that the devices were properly marked. Nonetheless, 35 U.S.C. § 287 (1994) limits only a patentee's ability to recover pre-notice damages. As discussed in detail above, without infringement and hence no damages, this court need not review the district court's holding on the issue of marking. Accordingly, this court vacates that holding.
COSTS
Each party to bear its own costs.
AFFIRMED IN PART and VACATED IN PART.