559 F.2d 611 | C.C.P.A. | 1977
This appeal is from the decision of the Patent and Trademark Office (PTO) Board of Appeals (“board”) affirming the rejection under 35 U.S.C. §§ 100 and 101 of claims 1, 2, 9, and 14-20
The Invention
The invention involves: a method for controlling a data processor to determine the relative numbers of O’s and l’s in a data word;
The method for determining the relative numbers of O’s and l’s in a data word is described in a prior opinion of this court, In re Waldbaum, 457 F.2d 997, 59 CCPA 940 (1972), involving this same application:
The process is carried out by taking particular advantage of two features allegedly available in at least certain prior art computers: a capability of handling what we shall call an EXAMINE instruction, and an address memory device referred to by appellant as a J-register.
The EXAMINE instruction causes the computer to perform several operations. First it examines the data word being analyzed and determines whether all the bits are 0’s. If the bits are all 0’s, the computer is instructed to jump to the address of that set of instructions which governs certain final calculation steps in appellant’s process. If the word contains one or more l’s, the EXAMINE instruction requires the computer to change the least significant 1 (the 1 appearing farthest to the right in the data word) to an 0. The computer then goes on to the instruction at the next consecutive address.
The J-register is a device which is used when there is a jump out of the regular order of instructions. Whenever an instruction requires the computer to go to an instruction address other than that of the next consecutive instruction, the address of the next consecutive instruction is recorded in the J-register. For example, assume that there is an EXAMINE instruction located at address number 100 in a computer, and that the address of the instruction governing the final calculations is address number 500. If the data word being analyzed is “0000” when the computer arrives at the EXAMINE instruction, the word will be analyzed, it will be determined that the word contains no l’s, and the computer will therefore be required to jump to the instruction at address number 500. Normally the computer would have followed the instructions in sequential order, i. e., it would have followed the instruction at address number 100, then followed the instruction at address number 101, etc. Since there has been a jump out of the sequential order, the address of the next consecutive instruction, address number 101, is stored in the J-register. In other words, whenever there is a jump, the J-register records the address the machine would have gone to next if there hadn’t been a jump.
The way appellant analyzes data words is by placing a number of EXAMINE instructions in consecutive addresses in a computer which has the J-register. As a*613 data word goes through the sequence of EXAMINE instructions, it loses its rightmost 1 as each instruction is carried out. Eventually the last 1 in the data word will be cancelled out. The next EXAMINE instruction will detect all 0’s in the word and will therefore cause the computer to jump to the instructions governing the final calculations. Since a jump is made, the address of the next consecutive instruction is placed in the J-register. The address of the last EXAMINE instruction used, minus the address of the first EXAMINE instruction in the sequence, gives the number of l’s which were contained in the data word.
As an example, the analysis of the data word “1010” could go as follows: Since the data word has only four digits, only four EXAMINE instructions will be necessary. These instructions must be placed in consecutive addresses in the computer’s memory, for example, at address numbers 100, 101, 102 and 103. When our data word is analyzed by the EXAMINE instruction at address number 100, it will be determined that not all of the bits are 0’s. The rightmost 1 will be changed to a 0, changing our word to “1000,” and the computer will go on to the instruction at address number 101. In following the EXAMINE instruction at address number 101, the computer will again find that not all of the bits in the word are 0’s, so that the computer will change the rightmost 1 to an 0, making our word now “0000,” and go on to the instruction at address number 102. In following the EXAMINE instruction at address number 102, the computer will find that all of the bits in our word are now 0’s. The address of the next consecutive instruction, 103, will therefore be placed in the J-register and the computer will jump to the instruction governing the final calculating steps. These final calculating steps constitute merely the manipulation of the number stored in the J-register and the address of the first EXAMINE instruction in the sequence. Since the address stored in the J-register (here 103) minus 1 always gives the point in the sequence where it was determined that all of the l’s had been changed to 0’s (here 102), that number minus the address of the first EXAMINE instruction in the sequence (100) will always give the number of l’s originally contained in the data word (2).
The above explanation of appellant’s process is at best vastly oversimplified, but it is enough to show the type of process we are dealing with, and that is all the background necessary here. [Id. 457 F.2d at 998-1000, 59 CCPA at 941-43.]
Specific application to counting the number of busy and idle lines in a telephone system entails assigning each bit in a particular data word the status of a telephone line. The bit is, for example, in the 1 condition if the respective line is busy and in the 0 condition if the line is idle. The number of l’s, or busy lines, at any point can then be counted.
Claims 1, 9, and 14 are illustrative of the claimed invention:
1. In the data processor of a processor-controlled telephone switching system having a register into which a bit pattern of l’s and 0’s respectively representing the busy and idle states of a plurality of telephone lines is entered, said data processor including a memory for storing data and instruction words at respective addresses; means for normally controlling the sequential execution of successively addressed instruction words; a plurality of registers; means for storing memory data words in said registers; means for performing logical operations on data words in said registers, said logical operations performing means including means for comparing the contents of predetermined ones of said plurality of registers; and means responsive to the execution of a predetermined instruction word for examining the data word contained in a predetermined first one of said registers, changing the rightmost 1 in said first register to a 0 if said register contains at least one 1, controlling a transfer to the instruction word at a spec*614 ified address in said data processor memory if said first register contains all 0’s, and storing in a predetermined second one of said registers the address of the following instruction word if said transfer is made;
a method of operating said data processor to count the number of busy ones of said telephone lines represented in said register comprising the steps of:
(1) controlling said storing means to store a memory data word whose number of l’s must be counted in said first register,
(2) controlling the data processor to execute a series of identical ones of said predetermined instruction word, and
(3) comparing in said comparing means the address of a first of the instruction words in said series with the content of said second register when a transfer is made during the execution of one of the instruction words in said series to derive the number of l’s in said data word.
9. A method for controlling the operation of a data processor to determine the relative numbers of 0’s and l’s in a data word; said data processor including a memory for storing data and instruction words at respective addresses; means for normally controlling the sequential execution of successively addressed instruction words; a plurality of registers; means for storing memory data words in said register; means for comparing the contents of predetermined ones of said plurality of registers; and means for controlling operations in the data processor in accordance with the instruction word being executed; comprising the steps of:
(1) controlling said storing means to store a memory data word whose relative numbers of 0’s and l’s must be determined in a first one of said registers;
(2) executing a series of identical instruction words, each of which controls the data word in said one register to have one of its bits of a predetermined value changed to the opposite value, and controls a transfer to be made to the instruction word at a specified address and the address of the next instruction word to be placed in a second of said registers if said first register contains bits of only said opposite value, and
(3) controlling said comparing means to compare the address of a predetermined one of the instruction words in said series with the content of said second register when a transfer is made during the execution of one of the instruction words in said series to determine the relative numbers of 0’s and l’s in said data word.
14. A process comprising a new use of a stored program data processing apparatus including an addressable memory for storing data words and instructions for processing said data words, means for executing said instruction, means for transferring to an instruction stored at a particular address as the result of executing said instructions and means for comparing data including said addresses obtained from said memory unit, said new use being the counting of the number of bits of a predetermined type in one of said data words and said process comprising the steps of:
a) executing one instruction of a series of instructions stored in successive addresses in memory for each bit of said predetermined type detected in said data word,
b) transferring to a return address when no more bits of said predetermined type are detected in said data word, and
c) comparing the addresses of the first and last executed ones of said instructions to compute the number of said predetermined type of bits in said data word.
Background
This is the second ex parte appeal to this court involving the present application. Prior to the first appeal, the board had sustained the rejection of all of the claims
This court reversed, concluding, with respect to the “mental steps” rationale, that “[i]t is clear that appellant’s process, which is useful in the internal operation of computer systems, is within the ‘useful arts’ ”, citing the court’s opinion in In re Benson, 441 F.2d 682, 58 CCPA 1134 (1971). In re Waldbaum, supra, 457 F.2d at 1003, 59 CCPA at 948.
Following reversal of this court’s decision in In re Benson by the Supreme Court (Gottschalk v. Benson, 409 U.S. 63, 93 S.Ct. 253, 34 L.Ed.2d 273 (1972) (hereinafter “Benson")), the PTO moved this court to vacate its decision in Waldbaum and to affirm the decision of the board. Appellant cross-moved for modification oí the court’s opinion and for confirmation and enforcement of the original decision. The motion and cross-motion were denied without additional comment.
Proceedings Below
After denial of the motions, the PTO reopened prosecution, and the examiner rejected all of the claims
[I]t is the position of the Primary Examiner that the holding of the Supreme Court in Benson effectively bars the grant of patent protection for subject matter of the nature disclosed by the present application. . . . The Benson opinion and that of the Court of Customs and Patent Appeals in In re Christensen [478 F.2d 1392, 178 USPQ 35 (1973)], make quite clear that a patent is not to issue where its effect would be to pre-empt, a mathematical formula or prevent others from making use of a mathematical procedure. The practical effect of allowing the claims on appeal would be a patent on the algorithm itself, a result in direct conflict with the express view of the Supreme Court.
The examiner noted that—
As claimed, appellant’s contribution, i. e. the novelty, is a program or procedure for the solution of a mathematical problem, namely, counting l’s in a data word. Although as claimed, the invention is embellished by the recitation of known “means” or elements, “new use” format, or stating what the l’s represent, the novelty, is, nevertheless, a procedure for solving a problem that is mathematical in nature. As such, the examiner contends that the Benson and Christensen decisions support the conclusion that the claims here on appeal are nonstatutory methods.
The board, although disavowing the examiner’s statement that the present issue is “independent of claim format,” agreed with the examiner’s reasoning and adopted the reasoning as its own.
OPINION
The sole issue is whether the claims define a statutory process within the meaning of 35 U.S.C. §§ 100 and 101, and, more specifically, whether the claimed subject
We agree with the PTO that allowance of the second and third groups, claims 9, 14-18, and 20, is proscribed by Benson. Claims 9, 16-18, and 20, are “so abstract and sweeping as to cover both known and unknown uses” of the method claimed. Cf. Benson, 409 U.S. at 68, 93 S.Ct. at 255. Claims 14 and 15 are even more “abstract and sweeping.” Although these two groups of claims are limited to the operation of data processing apparatus, the algorithm involved is not limited to any practical application other than in connection with such apparatus, and, therefore, a patent on these claims would in effect be a patent on the algorithm itself. As stated by the Supreme Court in Benson :
The mathematical formula involved here has no substantial practical application except in connection with a digital computer, which means that if the judgment below is affirmed, the patent would wholly pre-empt the mathematical formula and in practical effect would be a patent on the algorithm itself. [Id. at 71-72, 93 S.Ct. at 257.]
Appellant argues that he is not claiming a program, but rather a “machine process,” namely, a process of operating the machine in a new way. However, appellant’s problem is that patenting the “machine process” in practical effect would be a patent on the algorithm itself.
Appellant argues that these claims are distinguishable from those in Benson, since the latter were defined in terms of mathematical manipulation while the former recite specific machine steps. However, even though claims 9, 14-18, and 20 are not directed to an algorithm per se, their allowance would preempt use of the algorithm, as noted previously.
We note that claim 8 in Benson recited use of a “reentrant shift register,” which clearly is part of a machine process and not merely a mathematical manipulation. Although appellant argues that the Supreme Court treated both claims in Benson together, ignoring this machine limitation, he has not pointed to anything in the Benson opinion which supports this argument.
Claims 1, 2, and 19, which are limited to a method specifically applied to calculating the number of busy and idle lines in a telephone system,
In view of the foregoing, we hold that claims 1, 2, and 19 do not define a statutory process within the meaning of 35 U.S.C. §§ 100 and 101.
The Solicitor has further argued that a general-purpose digital computer is not a “particular” apparatus; that the Supreme Court, in Benson, supra, noted that “[transformation and reduction of an article ‘to a different state or thing’ is the clue to the patentability of a process claim that does not include particular machines” (Benson, id. at 70, 93 S.Ct. at 256); that appellant’s method merely provides an informational product without transforming any tangible material into a different state or thing; and that, consequently, appellant would have to rely on a “particular” machine to sustain any claims. However, in making the above-quoted statement in Benson with respect to the “clue to the patentability of a process claim”, the Supreme Court appears to have been referring to its “prior precedents.” Later in its opinion, the Court said:
It is argued that a process patent must either be tied to a particular machine or apparatus or must operate to change articles or materials to a “different state or thing.” We do not hold that no process patent could ever qualify if it did not meet the requirements of our prior precedents. It is said that the decision precludes a patent for any program servicing a computer. We do not so hold. [Emphasis added. Id. at 71, 93 S.Ct. at 257.]
Thus, the Supreme Court clearly did not say that only those process claims which are “tied to a particular machine or apparatus” or which “must operate to change articles or materials to a ‘different state or thing’ ” are statutory.
The decision of the board is affirmed.
AFFIRMED.
. In application serial No. 492,000, filed October 1, 1965, for “Method of Operating a Data Processor.”
. Each data word is composed of a plurality of bits (binary digits). Each bit has two output conditions, one of which, for our purposes, is labeled O and the other of which, for our purposes, is labeled 1. The method controls the data processor to determine the number of bits in the 1 condition and the 0 condition.
. In the first appeal, claims 14 and 15 recited a “new use” of a stored program data processing apparatus; the rest of the claims, although of varying breadth, were drawn to a method for controlling the operation of a data processor.
. The board also advanced three other grounds (not pertinent here) seemingly in support of its rejection under 35 U.S.C. §§ 100 and 101, which this court described as: (1) a “quasi-pri- or-art” theory; (2) a “quasi-indefiniteness” theory; and (3) an “alleged inadequate disclosure” theory. See In re Waldbaum, supra, 457 F.2d at 1000-01, 59 CCPA at 944-45.
. Present claims 14, 15, and 20 are identical (although claim 20 was renumbered) to claims previously before this court.
. Claim 1 recites in its preamble:
In the data processor of a processor-controlled telephone switching system having a register into which a bit pattern of l’s and 0’s respectively representing the busy and idle states of a plurality of telephone lines is entered, .
a method of operating said data processor to count the number of busy ones of said telephone lines represented in said register
Claim 2 is dependent from claim 1. Claim 19 recites in its preamble:
A telephone traffic counting method for determining the number of busy and idle lines in a telephone system in which a binary coded representation of the busy and idle states of a group of said lines is entered into a first register in the data processing unit of said telephone system .
The above-quoted portions of the preambles of these claims are repeatedly referred to in the method portion of each of the claims. Thus, such portions are necessary for completeness of the claims and are proper limitations thereto. See In re Higbee, 527 F.2d 1405, 1407 (CCPA 1976); Kropa v. Robie, 187 F.2d 150, 38 CCPA 858 (1951).
. Appellant’s specification states:
It is often necessary in computer-controlled systems to determine the number of l’s . . in a data word. An example is a telephone system .... [Emphasis added.] Clearly, appellant’s method of operating a data processor could be utilized in other computer-controlled systems wherein the controlled devices of the system can exist in one of two states.
